A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die; a second device die, stacked on the first device die; and first electrical connectors and second electrical connectors, disposed in between the first and second device dies. A first pitch between the first electrical connectors is greater than a second pitch between the second electrical connectors. The first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material. Each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material.

A wafer includes a substrate and conductive bumps on a surface of the substrate. In a plan view from a direction perpendicular to the surface of the substrate, the area density of the conductive bumps is higher in a first area than in a second area around the first area in the surface of the substrate. The first area has effective chip areas arranged therein.

A method of manufacturing an electronic device includes the following steps: providing an assembly comprising a substrate having a first die formed therein and having conductive areas positioned on a top surface thereof, a second die being mounted on the substrate and connected to the first die, the second die comprising through silicon vias; forming conductive pillars on the connection areas, an upper surface of the conductive pillars being flush with the second surface of the second die; forming a passivation layer on the substrate and on the second die; and forming conductive elements on the conductive pillars and on the vias, the periphery of the conductive elements covering the passivation layer.

A semiconductor package may include a first substrate; a second substrate on the first substrate; at least one chip structure on the second substrate; connection bumps below the first substrate; first bump structures between the first substrate and the second substrate; and second bump structures between the at least one chip structure and the second substrate, wherein each of at least a portion of the first bump structures and the each of at least a portion of the second bump structures includes a pillar bump, a solder ball connecting the pillar bump to one of the upper pads or upper terminals, and a barrier film at least partially covering a side surface of the pillar bump, and wherein a thickness of the barrier film decreases in a direction perpendicular to the side surface of the pillar bump in a portion adjacent to the solder ball.

A semiconductor device capable of suppressing a bonding defect between a bump of a semiconductor chip and a land of a wiring substrate is provided. The semiconductor device includes the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. The protective film is formed on the wiring layer so as to cover the first bonding pad and the second bonding pad. The protective film has a first opening portion overlapping the first bonding pad and penetrating through the protective film, and a second opening portion overlapping the second bonding pad and penetrating through the protective film.

A radio frequency module includes a module substrate having major surfaces that face each other, a first base part that is at least partially comprised of a first semiconductor material and in which an electronic circuit is formed, a second base part that is at least partially comprised of a second semiconductor material different from the first semiconductor material and in which a power amplifier is formed, and a switch connected to an output terminal of the power amplifier. The first base part is disposed on or over the major surface; the second base part is disposed between the module substrate and the first base part, is joined to the first base part, and is connected to the major surface via an electrode; and the switch is disposed on or over the major surface.

A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.

A semiconductor package includes a first semiconductor chip having a dummy region, a connection region, and a lower conductive structure disposed below the connection region; bump structures including a first bump structure on the lower conductive structure and a second bump structure below the dummy region; an interposer having the first semiconductor chip mounted thereon and upper conductive structures disposed in an upper portion thereof; connection bumps disposed on upper portions of the upper conductive structures: including a first connection bump in contact with the first bump structure and a second connection bump in contact with the second bump structure; and at least one second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip. The second bump structure includes a portion with a tapering width toward the second connection bump, an end of the second bump structure is inserted into the second connection bump.