A metal bump containing structure is provided which has a substantially flat top surface and enhanced coplanarity with other like metal bump containing structures. The metal bump containing structures include a metal bump having a curved top surface, and a first metal liner located along an outermost sidewall and present at least partially on the curved top surface of the metal bump.

A method of manufacturing a semiconductor device interconnect structure is provided. The method includes forming a copper pillar on a semiconductor die by way of a plating process. A proximal portion of the copper pillar has a first width dimension, and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be smaller than the first width dimension of the proximal portion of the copper pillar. Sidewalls of the distal portion of the copper pillar are selectively roughened. The roughened sidewalls of the distal portion of the copper pillar are configured to promote solder wetting.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A wafer includes a substrate and conductive bumps on a surface of the substrate. In a plan view from a direction perpendicular to the surface of the substrate, the area density of the conductive bumps is higher in a first area than in a second area around the first area in the surface of the substrate. The first area has effective chip areas arranged therein.

A semiconductor structure includes a semiconductor substrate, an insulating layer, a conductive feature and an anisotropic conductive structure. The insulating layer is disposed above the semiconductor substrate. The conductive feature is disposed in the insulating layer, wherein a top surface of the conductive feature is adjacent to a top surface of the insulating layer. The anisotropic conductive structure is disposed on the insulating layer and the conductive feature. The anisotropic conductive structure includes a metal oxide porous layer and conductive pillars. The metal oxide porous layer has a first nano-through-hole array exposing the top surface of the conductive feature and a second nano-through-hole array exposing the top surface of the insulating layer. The conductive pillars fill the first nano-through-hole array, wherein the conductive pillars are in contact with the top surface of the conductive feature.

A composite package may have a feature for enhancing thermal dissipation. The feature may include an array of metal pillar located on a backside a semiconductor die. Alternatively, the feature may include a cavity, to which a backside surface of a semiconductor die is exposed and which is laterally surrounded by a portion of a molding compound die frame.

A method for manufacturing a semiconductor device includes providing a semiconductor element having electrode terminals; forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminals and a second surface opposite to the first surface; forming an opening in the resist, which covers the electrode terminals by inserting protrusions of a mold into the resist above the electrode terminals; curing the resist by applying energy to the resist; and widening the opening in a radial direction of the opening. The resist is cured in a state where the second surface of the resist faces an inner surface of the mold with a gap between the second surface of the resist and the inner surface of the mold.

In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed; multiple copper posts coupled to the device side of the semiconductor die; a substrate coupled to the multiple copper posts by solder joints, the substrate comprising: cylindrical copper pillars extending from the solder joints on a top surface of the substrate to a bottom surface of the substrate, the copper pillars having circular or ovoid bottom surfaces exposed to the bottom surface of the substrate; and a build-up film between and physically contacting the copper pillars. The package also includes a mold compound physically contacting the semiconductor die, the multiple copper posts, and the top surface of the substrate.

An interconnect structure for advanced packaging and method for the interconnect structure are disclosed. The method includes: providing a semiconductor substrate to be packaged having surface on which there is a first pad having conduction-promoting surface; depositing a first passivation layer on surface of the semiconductor substrate, the first pad is exposed from first passivation layer, forming a wiring layer on surface of the first passivation layer by screen printing, and forming a metal layer on surface of the wiring layer by electroless plating, wherein the wiring layer covers the first pad; forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein there is a through hole in the second passivation layer, in which the metal layer is exposed; and forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole.

Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embodiment, the V-groove is free from conductive material. In an embodiment, the electronic device further comprises an optical fiber inserted into the V-groove.