A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

A method of manufacturing a semiconductor device interconnect structure is provided. The method includes forming a copper pillar on a semiconductor die by way of a plating process. A proximal portion of the copper pillar has a first width dimension, and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be smaller than the first width dimension of the proximal portion of the copper pillar. Sidewalls of the distal portion of the copper pillar are selectively roughened. The roughened sidewalls of the distal portion of the copper pillar are configured to promote solder wetting.

A semiconductor device has a substrate. The substrate is disposed on a quartz carrier. An electrical component is disposed over the substrate opposite the quartz carrier. An epoxy-solder paste bump is disposed between the substrate and electrical component. The epoxy-solder paste bump comprises an epoxy and a solder powder disposed in the epoxy. Laser energy is applied to a surface of the substrate through the quartz carrier. The laser energy is converted to thermal energy to reflow the solder powder and cure the epoxy.