A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer is exposed. An organic treatment is performed to the photoresist layer by a hydrophobic organic compound. After performing the organic treatment, the photoresist layer is developed. The material layer is etched using the photoresist layer as a mask.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

Semiconductor structures and fabrication processes are provided. A semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region.

A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O.sub.2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

A resist underlayer film-forming composition includes: a polymer; and a solvent, in which the polymer has, in a side chain, one or two or more polymerizable multiple bonds selected from the group consisting of a carbon-carbon double bond, a carbon-carbon triple bond, a carbon-nitrogen double bond, and a carbon-nitrogen triple bond.

A manufacturing method of a semiconductor device includes preparing a semiconductor substrate having an upper surface and a lower surface, forming a first mask having a plurality of openings on the upper surface divided into a first region and a second region, forming a second mask that exposes a portion of the first mask arranged in the first region and covers a portion arranged in the second region, etching the semiconductor substrate in the first region using the first mask and the second mask as a mask, removing the second mask, and etching the semiconductor substrate in the first region and the second region using the first mask as a mask.

Disclosed is a method for fabricating a semiconductor device that improves a Self-Aligned Contact (SAC) margin by applying a wave-shaped buried gate. The method includes forming an isolation layer over a substrate and active regions defined by the isolation layer, forming a first hard mask pattern having a protrusion extending in a first direction over the substrate and overlapping with both ends of the active regions, forming a trench having a plurality of concave portions crossing the active regions and the isolation layer in the first direction and overlapping with the active regions by etching the substrate, and forming a buried gate structure to gap-fill the trench. The active regions are disposed in a first direction and a second direction orthogonal to the first direction and tilted in a third direction diagonal to the first and second directions.

Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.

Methods for full hard mask removal and a semiconductor structure are presented. A semiconductor structure comprises a base layer of dielectric material; a body layer of a low-k dielectric material over the base layer; a hard mask over the body layer; and a plurality of trenches etched through the hard mask and the body layer and only partially etched into the base layer.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.