A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.