A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.

A method includes forming first and second TFR contacts spaced apart in a dielectric region, forming a dielectric barrier layer over the TFR contacts, and removing a region of the dielectric barrier layer to define an opening defining a pair of lateral edges of the dielectric barrier layer extending between the first and second TFR contacts. An etch is performed through the opening to define a TFR cavity including respective undercut cavity regions extending laterally below the dielectric barrier layer near each of the lateral edges. A TFR material is deposited in the TFR cavity to define a TFR element layer including (a) a TFR element base defining a pair of end edges adjacent the first and second TFR contacts, and a pair of side edges extending between the end edges; and (b) a pair of TFR element end ridges extending upwardly from the end edges of TFR element base.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.