A power electronics module, having a continuous DBC PCB having power semiconductors arranged on connecting regions of an uppermost layer of said DBC PCB and a lead frame arranged above the power semiconductors for three-dimensional power and control routing, wherein the lead frame has a drain-source connection, which can be brought into electrical contact with a drain-source contact of the PCB, and a load-source connection which is opposite the drain-source connection via the power semiconductors and which is formed from a plurality of subregions, each of which can be brought into electrical contact with one of the power semiconductors, and at least one gate-source terminal and at least one kelvin-source terminal, and a carrier element including an electrically insulating material on which conductor tracks are provided, wherein the carrier element is routed between the power semiconductors in a region between the load-source connection and the drain-source connection.

A switching power device comprises a device lead-frame. Gates, Kelvin sources and a drain are formed on the device lead-frame, the gates and the Kelvin sources are arranged at one end of the device lead-frame, and the drain is arranged at the other end of the device lead-frame; and two gates and two Kelvin sources are provided. One end of the device lead-frame is sequentially provided with the gate, the Kelvin source, the Kelvin source and the gate, so as to form a symmetrical pin structure.

An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

A semiconductor device having a fan-out package structure includes a semiconductor element having a first electrode pad and a second electrode pad on a front surface, a sealing material covering a side surface of the semiconductor element and a redistribution layer covering the front surface of the semiconductor element and a part of the sealing material. The redistribution layer includes an insulation layer, a first redistribution wire and a second redistribution wire. At least a part of the first redistribution layer is disposed above a boundary between the side surface of the semiconductor element and the sealing material. The second redistribution wire is electrically connected to the second electrode pad, and at least has a part that extends to a position outside of a contour of the semiconductor element over the first redistribution wire. The second redistribution wire is electrically independent of the first redistribution wire.

An electronic device includes a package structure, a lead, a heat slug, a semiconductor die, and a bond wire. The package structure has opposite first and second sides, and opposite third and fourth sides spaced along a first direction. The heat slug has a first portion partially exposed outside the second side of the package structure, and a second portion with slots extending inwardly along the first direction and fins between respective pairs of the slots, where the fins are enclosed by the package structure and spaced along an orthogonal second direction. The semiconductor die is attached to the heat slug, and the bond wire has a first end connected to the lead and a second end connected to a circuit of the semiconductor die.

An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

A transistor through-hole package module includes: an insulating package body and at least one transistor encapsulated therein; a lead frame including through-hole pins extending from the insulating package body and a die pad disposed within the insulating package body. The transistor is mounted on the die pad and electrically connected to the through-hole pins; a metal heat sink plate that is partially exposed from the insulating package body. Both the metal heat sink plate and the lead frame are formed of copper or copper alloy, and the side of the lead frame facing away from the transistor is bonded to the metal heat sink plate via a thermally conductive insulating adhesive. The package module of the present disclosure offers the advantage of superior heat dissipation performance.

A method includes providing an IC package having a lead and a die encapsulated in a mold compound. The mold compound extends from a top mold surface to a base mold surface of the IC package. The method also includes trenching the mold compound from the top mold surface to the lead to form a trench. The method further includes forming a vertical wettable flank by filling the trench with a conductive material.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.