Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.

An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.

The disclosure describes a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes: a first module and a second module stacked vertically on the first module, each module includes multiple dies stacked vertically within an insulation layer, wherein each die higher than a lower die is laterally offset from the lower die forming a terraced structure, wherein the second module comprises vertical wires connecting the overhang portions of the terraced structure of the second module to a top dielectric layer of the first module underneath the second module, and the insulation layer of the first module further includes through-insulation vias (TIVs) connecting the top dielectric layer to a bottom dielectric layer through the insulation layer, such that the dies of the second module are coupled to the bottom dielectric layer of the first module through the top dielectric layer and TIVs.

A package comprising a first integrated device; a second integrated device coupled to the first integrated device through an adhesive; a first plurality of wire bonds coupled to the first integrated device; a second plurality of wire bonds coupled to the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, the first plurality of wire bonds and the second plurality of wire bonds; and a plurality of pillar interconnects.

A semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first die and offset from it in a first direction and a second direction that are perpendicular to each other, and a third semiconductor die stacked on the first and second dies and offset from them in the first direction. The first semiconductor die includes a first pad and a second pad, arranged successively in the second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each arranged successively in the second direction. A first conductive pattern connects the first and fifth pads, while a second conductive pattern connects the second, fourth, and sixth pads. The first and second conductive patterns are spaced apart from the third pad.

An embodiment provides a semiconductor package including a package substrate including substrate pads, and a chip stack including a plurality of semiconductor chips stacked on the package substrate, wherein the plurality of semiconductor chips include first and second semiconductor chips having the same size and shape device region, the first and second semiconductor chips include first and second chip pad regions protruding from different regions of a first side of the device region, respectively, and each chip pad being connected to a substrate pad by a wire, and the first and second semiconductor chips are stacked such that the first and second chip pad regions face in the same horizontal direction and do not overlap each other in a stacking direction.