A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.

A semiconductor package may include a first redistribution structure, a sub-semiconductor package on the first redistribution structure, where the sub-semiconductor package may include a second redistribution structure, a bridge die on the second redistribution structure, a first molding material configured to cover the bridge die on the second redistribution structure, a third redistribution structure on the first molding material and on the bridge die, a first semiconductor die on the third redistribution structure, a second semiconductor die on the third redistribution structure, and beside the first semiconductor die, where the second semiconductor die is electrically connected to the first semiconductor die through the bridge die, and a second molding material configured to cover the first semiconductor die and the second semiconductor die, on the third redistribution structure, and a third molding material configured to cover the sub-semiconductor package, on the first redistribution structure.

A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.

A semiconductor package includes a substrate including a first surface and a second surface, and a first substrate pad on the second surface, a first semiconductor chip on the second surface and including a third surface and a fourth surface, a first hotspot within the first semiconductor chip, and a first chip pad on the fourth surface, a first dummy pad on the fourth surface, a first layer connecting the first hotspot and the first dummy pad, a first pillar on the first dummy pad, a mold film on the substrate and including a fifth surface and a sixth surface, a thermal interface material layer on the mold film, and a heat slug on the thermal interface material layer; the mold film includes a first recess recessed inwardly from the sixth surface of the mold film, and at least part of the thermal interface material layer is in the recess.

A semiconductor package includes a redistribution layer (RDL) including a redistribution wiring structure, a first semiconductor chip on the RDL and electrically connected to the redistribution wiring structure, a heat dissipation member in contact with an upper surface of the first semiconductor chip, a conductive post on the RDL and spaced apart from the first semiconductor chip in a horizontal direction, the conductive post being electrically connected to the redistribution wiring structure, a first molding member on the RDL configured to cover at least a portion of a sidewall of the first semiconductor chip and a sidewall of the conductive post, a package substrate in contact with an upper surface of the heat dissipation member and electrically connected to the conductive post, a second semiconductor chip on and electrically connected to the package substrate, and a second molding member on the package substrate and configured to cover the second semiconductor chip.

Method for manufacturing a thermal interface film, the method comprising: providing a template comprising a plurality of openings through the template; arranging graphene fibers through the openings; attaching a support plate on at least one side of the template such that the graphene fibers are attached to the support plate; removing the template to expose the graphene fibers; infiltrating the graphene fibers with a polymer material to form a block of polymer infiltrated graphene fibers; and cutting the block of polymer infiltrated graphene fibers along a direction perpendicular to the extension of the graphene fibers to form a thermal interface film.

A heat conduction sheet includes a heat conduction layer containing at least one kind of graphite particles (A) selected from the group consisting of scale-like particles, ellipsoidal particles and rod-like particles, wherein in a case of scale-like particles, a plane direction of the particle is oriented in a thickness direction of the heat conduction sheet, and in a case of ellipsoidal particles or rod-like particles, a long axis direction of the particle is oriented in the thickness direction of the heat conduction sheet, and the heat conduction sheet contains a metal component having a melting point of 200 C. or less.

The composite filler filler forms a core-shell structure composed of a core substance made of carbon, metal, zinc oxide or zirconium oxide and a shell substance attached to a surface of the core substance. The shell substance is formed from fumed oxide particles, the fumed oxide particles being attached to a part or a whole of the surface of the core substance by mixing of the fumed oxide particles and the core substance in a dry ball mill. The fumed oxide particles are particles changed from bulky aggregated particles to gathered bulk particle. In the composite filler, percentage of the core substance ranges from 30 vol % to 85 vol % and percentage of the shell substance ranges from 15 vol % to 70 vol %, a thermal conductivity is 0.075 W/m.Math.K or more, a volume resistivity is 1.010.sup.5 .Math.cm or more, and a dielectric breakdown voltage is 1 kV/mm or more.

A method of manufacturing a heat sink-integrated power module substrate according to an embodiment of the present disclosure may include preparing a ceramic heat sink, forming a pattern of a conductive material on a top surface of the ceramic heat sink, and forming an electrode pattern by firing the conductive material. Here, the pattern of the conductive material may be formed on the top surface of the ceramic heat sink using screen printing.