An electronic device includes a substrate, a support body, and a conductive film. The substrate is a piezoelectric substrate or a compound semiconductor substrate including a first main surface with functional elements. The support body is provided at a second main surface of the substrate opposite to the first main surface and has a higher thermal conductivity than the substrate. The conductive film is located in a through hole extending through the support body and has a higher thermal conductivity than the support body.

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

An integrated device package includes a substrate and a die coupled to the substrate. The integrated device package also includes a thermal interface material coupled to the die, and a lid coupled to the substrate and to the thermal interface material. The lid includes a unitary body that includes one or more openings that define a die contact area of the unitary body and one or more compliant members of the unitary body.

An electronic device includes a first substrate structure, a first circuit structure and a package structure. The first circuit structure is disposed on a surface of the first substrate structure, and the first circuit structure includes a first substructure. The package structure is disposed on the first circuit structure and electrically connected with the first circuit structure. The first substructure has a first coefficient of thermal expansion, the package structure has a second coefficient of thermal expansion, and a ratio of the second coefficient of thermal expansion to the first coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.5.

An electrical connection device includes: a printed circuit board; a probe head holding a plurality of probes, each of the probes having a proximal end portion that is electrically connected to the printed circuit board and a distal end portion that comes into contact with an inspection target object; and a fix base provided below the printed circuit board and partially fixed to an upper surface of the probe head. The fix base and the printed circuit board are relatively movable according to thermal expansion.

A semiconductor package includes a substrate, a package, a plurality of semiconductor devices, and a thermal dissipating module. The package is disposed over and electrically coupled to the substrate, and includes a plurality of dies. The semiconductor devices are disposed over and electrically coupled to the substrate and laterally next to the package. The thermal dissipating module is disposed over the substrate and includes a first thermal dissipating element connected to and thermally coupled to the package through a first thermal interface material and a second thermal dissipating element connected to and thermally coupled to the semiconductor devices through a second thermal interface material, where a thermal conductivity of the first thermal interface material is different from a thermal conductivity of the second thermal interface material.

The present invention relates to a power module comprising: a lower ceramic substrate (200); an upper ceramic substrate (300) which is disposed above the lower ceramic substrate (200) and has a semiconductor chip (G) mounted on the lower surface thereof; a PCB substrate (400) disposed above the upper ceramic substrate (300); and a connection pin (800) which extends through through holes (320 and 420) formed in the upper ceramic substrate (300) and the PCB substrate (400), and vertically connects electrode patterns (a, b, c, and d) formed on the upper ceramic substrate (300) and the PCB substrate (400). The present invention provides a shortened electrical connection distance between the upper ceramic substrate and the PCB substrate, and thus can minimize a current path and enhance the moving efficiency of a high-speed current.

The present invention relates to a power module and a method for manufacturing same, the power module including: a lower ceramic substrate; an upper ceramic substrate which is disposed spaced apart from the upper portion of the lower ceramic substrate, and on the lower surface of which a semiconductor chip is mounted; spacers each having one end bonded to the lower ceramic substrate and the other end bonded to the upper ceramic substrate; first bonding layers each bonding the one end of each spacer to the lower ceramic substrate; and second bonding layers each bonding the other end of each spacer to the upper ceramic substrate. The present invention maintains a constant distance between the lower ceramic substrate and the upper ceramic substrate by having the spacers arranged therebetween, and thus is advantageous in that the semiconductor chip can be protected and heat dissipation efficiency can be increased.

A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.

A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.