A method comprises: covering at least part of the integrated circuit with a material, the material including an opening that penetrates through the material; and forming a layer of nanoparticles on at least part of an internal wall of the opening and over at least part of the integrated circuit.

An insulating substrate in which one principal surface of a heat-dissipation-side metal plate is brazed to one principal surface of a ceramic substrate via a brazing material layer provided therebetween, in which a Ni plating layer that covers the brazing material layer exposed between the ceramic substrate and the heat-dissipation-side metal plate is provided, and at least a portion of the other principal surface of the heat-dissipation-side metal plate is not covered with a Ni plating layer, leaving the surface of the heat-dissipation-side metal plate exposed. According to the present invention, it becomes possible to obtain the insulating substrate having excellent furnace passing resistance of the insulating substrate (alone) and further having excellent heat cycle characteristics in a state of a heat sink plate being soldered to the insulating substrate.

An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.

A chip includes an active device, a first backside thermally conductive layer, and a second backside thermally conductive layer, wherein the first backside thermally conductive layer is between the active device and the second backside thermally conductive layer. The chip also includes a first via electrically coupled to the active device, wherein the first via extends through the first backside thermally conductive layer, and a first metal path electrically coupled to the first via, wherein the first metal path extends through the second backside thermally conductive layer.

A power module, can include: a substrate, including an interior having at least one bare die, and a top surface having a first pad; at least one inductor structure disposed on the top surface of the substrate, being configured to electrically connected to the bare die via the first pad, and having a magnetic core; and a thermal conductive structure, including a first portion formed between the top surface of the substrate and a bottom surface of the magnetic core, a second portion extending from the bottom surface of the magnetic core to a top surface of the magnetic core, and a third portion formed on the top surface of the magnetic core, where the first portion, the second portion, and the third portion are connected together.

A semiconductor device includes: a substrate with a circuit pattern: a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame member including a wall portion; and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion, and a second region continuous to the first region and located inside the frame member. A distance between an inner wall surface of the wall portion and the circuit pattern is 500 m or less. The second region is directly connected to the circuit pattern.

Various examples relate to a diamond-based film for a die stack, to a method for forming a diamond-based film for a die stack, and to a die stack comprising at least one diamond-based film. The diamond-based film comprises a plurality of laser-induced graphitic structures configured to provide electrical connectivity between a first semiconductor die and a second semiconductor die arranged adjacent to the diamond-based film in the die stack.

A system includes at least one component package. Each of the component packages includes at least one electronic component such as a semiconductor component. Each component has a first outer surface and a second outer surface facing away from the first outer surface.

Improved cooling efficiency and simplified manufacture are achieved by providing a cooler for at least one of the outer surfaces of the components. A flow path in the cooler substantially locally extends over the associated outer surface.

A spherical alumina powder, wherein D50 is 0.1 to 40 m; a circularity is 0.90 or more and 1.00 or less; an -phase percentage is 60% or more and 100% or less; and a particle surface roughness represented by Equation (1) below is 1.14 or more and 1.35 or less:

[00001]$\begin{array}{cc}\mathrm{Particle}\mathrm{surface}\mathrm{roughness}=\mathrm{BET}\mathrm{specific}\mathrm{surface}\mathrm{area}A/\mathrm{sphere}-\mathrm{equivalent}\mathrm{specific}\mathrm{surface}\mathrm{area}\mathrm{Sa}\mathrm{calculated}\mathrm{from}\mathrm{particle}\mathrm{size}\mathrm{distribution}.& \mathrm{Equation}\left(1\right)\end{array}$

A heat dissipating member includes: a sintered material portion containing copper and at least one of tungsten and molybdenum; and a plurality of silicon oxide particles dispersed in the sintered material portion. The heat dissipating member has a copper content of M.sub.Cu weight percent, a tungsten content of M.sub.W weight percent, a molybdenum content of M.sub.Mo weight percent, and a silicon oxide content of M.sub.SiO2 weight percent in terms of SiO.sub.2 equivalent, relative to a total weight of copper, tungsten, and molybdenum. The heat dissipating member satisfies: 0.9M.sub.Cu/(M.sub.Cu+M.sub.W+M.sub.Mo)0.045; and 0.01M.sub.SiO2/(M.sub.Cu+M.sub.W+M.sub.Mo)0.0003.