A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

A wafer-to-wafer bonding structure includes a first wafer having a first bonding layer thereon, a first main pattern region, a first scribe lane surrounding the first main pattern region, and a first alignment cavity disposed in the first bonding layer within the first main pattern region; and a second wafer having a second bonding layer bonded to the first bonding layer, a second main pattern region, a second scribe lane surrounding the second main pattern region, and a second alignment cavity disposed in the second bonding layer within the second main pattern region.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A hollow package includes a device substrate; a lid substrate provided above the device substrate; a first sealing ring provided on an upper surface of the device substrate; a second sealing ring provided on a lower surface of the lid substrate so as to face the first sealing ring; a seal layer that bonds the first sealing ring and the second sealing ring; and a functional element provided in a hollow portion surrounded by the device substrate, the lid substrate, the first sealing ring, the second sealing ring, and the seal layer, wherein the first sealing ring or the second sealing ring has a corner portion in a planar view, and the first sealing ring or the second sealing ring has a recess, which is recessed in a direction perpendicular to the upper surface of the device substrate, locally formed in a portion including the corner portion.

A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.