A semiconductor module includes a plate-shaped base made of metal, and a frame-shaped housing made of a resin composition, the housing having an adhering portion adhering to an outer peripheral portion of the base, wherein in plan view, an outer periphery of the housing includes first sides facing each other and second sides facing each other, a portion of the housing corresponding to each of the second sides is provided with at least one hole for screwing a heat dissipating member, the adhering portion includes a plate-shaped first adhering portion extending along each of the first sides, in plan view, the first adhering portion overlaps an outer periphery of the base, and inequality T.sub.1<0.42L.sub.1.sup.2 is satisfied, when T.sub.1 is T.sub.1 meters that denote a thickness of the first adhering portion, and L.sub.1 is L.sub.1 meters that denote a length of the first adhering portion.

A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.

A high bandwidth memory including a first semiconductor stack including a plurality of first semiconductor dies stacked in a vertical direction; a glass core on the first semiconductor stack; and a second semiconductor stack on the glass core, the second semiconductor stack including a plurality of second semiconductor dies stacked in the vertical direction.

The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

A semiconductor device includes: a heat dissipation base; a case including an outer peripheral wall that has an inner surface facing an inside of the case and a wiring terminal provided integrally with the outer peripheral wall, the wiring terminal having an inner end portion, which is on one end of the wiring terminal and is exposed to the inside of the case from the inner surface of the outer peripheral wall; a sealing member sealing the inside of the case; and an adhesion member embedded in the inner surface of the case and having an adhesion surface exposed from the inner surface, the adhesion member and the heat dissipation base being on different sides of the inner end portion. The adhesion surface has higher adhesion to the sealing member than the outer peripheral wall.

An electronic device includes a multilevel ceramic body, first, second, and third plates, and first and second semiconductor dies, with the multilevel ceramic body having opposite first and second sides, a first and second openings in the first side, a third opening in the second side, and a ceramic separator structure defining first and second interior portions between the first and second openings. The first plate is attached to the first side and covers the first opening, the second plate is attached to the first side and covers the second opening, the third plate is attached to the second side and covers the third opening, the first semiconductor die is in the first interior portion, and the second semiconductor die is in the second interior portion of the ceramic body.

Technologies for through-glass vias with caps are disclosed. In an illustrative embodiment, a substrate core has holes defined in it, and vias are positioned in the holes to carry power or data signals through the substrate core. The vias are formed using bottom-up plating, forming vias that are not anchored to the sidewalls of the holes in the substrate core. The vias can thus move relative to the substrate core, which can mitigate cracking of the core during thermal cycling. In order to mitigate cracking in the build-up layers on the core, the via has a via cap, which can reduce the stress in the build-up layers. Various configurations of such vias are disclosed, and various approaches to fabricate such vias are disclosed.