An electronic component including a first device die hybrid bonded to a carrier, an encapsulant encapsulating side surfaces of the first device die and a cover element disposed over directly bonded to a top surface of the first device die. The encapsulant comprises particles embedded therein, and wherein an interface between a top surface of the encapsulant and a bottom surface of the cover element lacks ground particles

A photoelectric conversion apparatus includes a first chip having a first semiconductor element layer including a pixel region of a plurality of pixel circuits, and a second chip having a second semiconductor element layer. The first and second chips are bonded by a plurality of metal bonding portions between the first and second semiconductor element layers. The plurality of metal bonding portions includes first and second metal bonding portions disposed in a region overlapping with the pixel region in a plan view. The first metal bonding portion connects at least either one of the plurality of pixel circuits and the second semiconductor element layer. The second metal bonding portion is connected to at least either one of the plurality of pixel circuits and is not connected to the second semiconductor element layer in the region overlapping with the pixel region.

A device may include a substrate comprising a plurality of first contact pads disposed on a first surface, and a plurality of second contact pads disposed on a second surface, the substrate comprising a plurality of interconnect structures extending between the first surface and the second surface. A device may include a first portion of an axial extension of the plurality of interconnect structures having sidewalls of a first profile. A device may include a second portion of the axial extension of the plurality of interconnect structures having sidewalls of a second profile, shallower than the first profile.

A semiconductor package may include a base chip, a semiconductor chip stack including a plurality of semiconductor chips sequentially stacked on the base chip, a plurality of connection bumps below the base chip, and an encapsulant covering a side surface of the first semiconductor chip and side surfaces of each of the plurality of second semiconductor chips on the base chip, wherein, on at least one side of the semiconductor chip stack, the encapsulant includes a portion in which a width thereof in a horizontal direction increases as the encapsulant being away from the base chip in a vertical direction.

According to one aspect of the present disclosure, a memory apparatus is provided. The memory apparatus may include a first memory die and a die group stacked in a first direction. The die group may include M second memory dies stacked in the first direction. Each of the second memory dies may be connected to a third memory die and configured to perform data exchange at a bandwidth of (N*X) bits with the third memory die through N data channels. The first memory die may be connected to the third memory die. The first memory die may be configured to perform data exchange at a bandwidth of (N*X) bits with the third memory die through N data channels. The first memory die may be configured to replace a first data channel of the die group when a storage portion corresponding to the first data channel fails.

A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.

A semiconductor device is disclosed. The semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface, and a first conductive film, which is electrically connected to the package substrate and is extended to a region on the first side surfaces of the semiconductor chips. Each of the semiconductor chips may include a peripheral circuit structure including first bonding pads on a first surface of a substrate, a first cell array structure including a first stack and second bonding pads bonded to the first bonding pads, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film.

The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.

A film package includes a base film including peripheral regions on opposite ends of the base film in a width direction and extending in a lengthwise direction, an inner region between the peripheral regions and extending in the lengthwise direction, and sprocket holes provided on the peripheral regions at a regular interval in the lengthwise direction, and a unit film package provided on the base film and defined by a cut line, the unit film package including a mount region on the inner region and a connection region provided in the lengthwise direction from the mount region, the connection region extending from the inner region toward a location between the sprocket holes in the lengthwise direction.