Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

The present disclosure provides a manufacturing method of a semiconductor structure including the following steps. A trench is formed between bit lines. A seed layer is deposited in the trench, and a first contact layer is deposited on the seed layer in the trench. A second contact layer is deposited on the first contact layer to fill the trench, in which a second doping concentration of the second contact layer is lower than a first doping concentration of the first contact layer. An annealing process is performed on the first contact layer and the second contact layer, such that dopants in the first contact layer diffuse into the second contact layer to form a contact plug including the first contact layer and the second contact layer.

Various embodiments include methods and apparatuses to moisturize a substrate prior to an electrochemical deposition process. In one embodiment, a method to control substrate wettability includes placing a substrate in a pre-treatment chamber, controlling an environment of the pre-treatment chamber to moisturize a surface of the substrate; and placing the substrate into a plating cell. Other methods and systems are disclosed.