A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

A workpiece handling apparatus includes a workpiece chuck, and a robotic device. The workpiece chuck is for holding a workpiece thereon, wherein the workpiece chuck includes a porous supporting platform, a gas permeable buffer layer covering a supporting surface of the porous supporting platform, and a vacuum system in gas communication with the porous supporting platform and the gas permeable buffer layer. The robotic device is movably disposed over the workpiece chuck for picking up the workpiece and placing the workpiece on the gas permeable buffer layer.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

A semiconductor device for a power conversion circuit includes a first main terminal, a second main terminal, a signal terminal, a substrate, a semiconductor element and a snubber circuit. The substrate has an insulating base material, a first wiring disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring disposed on the one surface and electrically connected to the second main terminal. The semiconductor element is electrically connected to the first wiring. The snubber circuit includes a capacitor and electrically bridges the first wiring and the second wiring. The substrate has a signal wiring that is disposed between the semiconductor element and the snubber circuit and electrically connects the signal terminal and the semiconductor element.