A semiconductor device comprising a terminal, a semiconductor element and a sealing resin. The semiconductor element is disposed on one side of the terminal in a first direction and electrically connected to the terminal. The sealing resin covers the semiconductor element and a part of the terminal. The sealing resin has a bottom surface disposed on an opposite side to the semiconductor element with respect to the terminal in the first direction. The terminal extends beyond the bottom surface.

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.

A power semiconductor module includes an AC bus bar having a first side that faces a first substrate and a second side that faces a second substrate. A first power transistor die has a drain terminal connected to a first metallic region of the first substrate and a source terminal connected to the first side of the AC bus bar. A second power transistor die has a drain terminal connected to the second side of the AC bus bar and a source terminal connected to a first metallic region of the second substrate. First and second DC bus bars are connected to the first metallic region of the respective substrates, vertically overlap one another, and protrude from a first side of a mold body that encapsulates the power transistor dies. The AC bus bar protrudes from a different side of the mold body as the DC bus bars.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

A semiconductor device includes a chip carrier, a first power chip arranged above a mounting surface of the chip carrier, a laminate arranged above a top surface of the first power chip facing away from the chip carrier, and a first logic chip configured to drive the first power chip and arranged above a top surface of the laminate facing away from the chip carrier. The first power chip and the first logic chip are electrically coupled via an electrical wiring of the laminate.