Patent classifications
H10W20/4446
Chip Metallization Method and Chip
A chip includes a chip substrate having a first thickness and including a back surface. The back surface includes an etched portion with an etching depth that is less than the first thickness. The chip further includes a first thin film including a dielectric material and located on the back surface. The chip further includes a second thin film including a barrier layer material and located on the first thin film. The chip further includes a third thin film including a metal material, embedded in the chip substrate, and located on the second thin film. The chip further includes a coverage layer including nitride or carbon nitride and located on the first thin film, the second thin film, and the third thin film.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present invention relates to a semiconductor device with improved reliability and a method for manufacturing the same. A semiconductor device according to the present invention may comprise: a substrate including a gate trench; a gate insulating layer formed on a surface of the gate trench; and silicon-doped metal nitride on the gate insulating layer, wherein the silicon-doped metal nitride has a silicon concentration of less than 1 at %.
Interconnects including graphene capping and graphene barrier layers
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
A pre-cleaning operation, using a metal-precursor, is performed to remove a metal-oxide layer from a top surface of a contact structure of a semiconductor device prior to forming a conductive structure of the semiconductor device on the contact structure. The use of the metal precursor as a pre-cleaning agent for the pre-cleaning operation enables native oxides to be fully removed (not just constituent parts such as oxygen) without causing the formation of pores in the top surface of the contact structure, which enables a low contact resistance to be achieved between the contact structure and the conductive structure.
INTERCONNECT STRUCTURE HAVING METAL FEATURES WITH DIFFERENT VOLUME AND MATERIALS, AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing an interconnect structure includes: forming a base structure; forming a first metal feature on the base structure, the first metal feature having a first volume and including a first metallic material; forming a first dielectric layer surrounding the first metal feature and over the base structure; and forming a second metal feature in the first dielectric layer, the second metal feature being spaced apart from the first metal feature, having a second volume greater than the first volume, and including a second metallic material different from the first metallic material.