Provided is an evaluation method of a semiconductor substrate, including: implanting hydrogen ions from an implantation surface of a semiconductor substrate containing silicon; annealing the semiconductor substrate; measuring a differential carrier concentration, which is a difference between a first carrier concentration in a passage region of the semiconductor substrate through which the hydrogen ions have passed and a second carrier concentration in a non-passage region of the semiconductor substrate where the hydrogen ions have not reached; and evaluating a carbon concentration in the semiconductor substrate, based on the differential carrier concentration.

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

A semiconductor device structure includes: a first source/drain feature over a first device region of a substrate; first semiconductor layers over the first device region, each first semiconductor layer being in contact with the first source/drain feature; a first gate electrode layer surrounding the first semiconductor layers; and a first dielectric spacer contacting the first source/drain feature and being disposed between and in contact with two of the first semiconductor layers. The substrate includes a first dopant region underneath the first source/drain feature and a second dopant region underneath the first gate electrode layer and radial outwardly of the first dopant region. The first dopant region includes first dopants having a first conductivity type and a first dopant concentration and the second dopant region includes the first dopants having a second dopant concentration less than the first dopant concentration.

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

A method for manufacturing a memory device includes providing a substrate, an array region of the substrate includes a central region and an edge region surrounding the central region, and the substrate includes a first active region and a second active region separated by an isolation structure. The method includes sequentially forming a bit line contact and a bit line structure over the first active region, conformally forming a dielectric liner on the substrate to cover the bit line contact and the bit line structure, and performing an etching process on the substrate to form a trench and expose the second active region. The method further includes performing an ion implantation process on the trench in the edge region to form an insulating layer at a bottom of the trench and covering the second active region, and forming a capacitor contact structure over the second active region.

Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.