An electronic component manufacturing method for obtaining an electronic component in which a resin molded body and an object are integrally formed and the resultant device is provided. The method includes forming a resin distribution set by feeding a resin material in granular, powder, or liquid form onto a release film in a resin receiving portion to create a non-uniform distribution, wherein the resin material is thicker at a predetermined location than at other locations. The resin distribution set including the release film and placing the resin distribution set onto a lower mold such are lifted and placed over a cavity in a lower mold. The release film covers an inner surface of the cavity, positioning the resin material in the cavity. The resin material is compression-molded with the object in contact with the resin material located in the cavity to obtain the device.

An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

A method of manufacturing a semiconductor package includes disposing a substrate strip having a plurality of semiconductor chips in a bottom mold, the bottom mold including sets of injection holes arranged on one side of the substrate strip, coupling the bottom mold and a top mold to contact each other, the top mold including cavities open toward corresponding ones of the sets of injection holes, individually injecting a first molding material and a second molding material into each of the cavities through injection holes included in a corresponding one of the sets of injection holes, respectively, forming a molding compound including the first molding material and the second molding material in the cavities, separating the top mold and the bottom mold from each other, curing the molding compound covering the semiconductor chips to form a mold structure, and cutting the mold structure.

A release film, method for producing the same, and packaging apparatus are provided. The release film includes a PET base layer and a release layer. The release layer is formed by coating a coating liquid onto the PET base layer. The coating liquid includes a base material having a glass transition temperature (Tg) of between 60 C. and 30 C. and a plurality of inorganic particles dispersed in the base material. An average particle size of the inorganic particles is between 8 m and 12 m. A thickness of the release layer is between 5 m and 20 m, and a surface roughness (Ra) of the release layer is between 0.4 m and 0.8 m. The release layer is configured to be in contact with an epoxy resin, and a release force between the release layer and the epoxy resin is between 50 gf/inch and 400 gf/inch.

A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a top surface and a bottom surface; a top electronic component mounted on the top surface of the substrate; at least one conductive pillar formed on the bottom surface of the substrate; and a protection layer attached on the bottom surface of the substrate and covering the at least one conductive pillar; providing a molding apparatus including a top chase and a bottom chase, wherein a molding material is held in the bottom chase; attaching the protection layer onto the top chase of the molding apparatus; and moving the top chase and the bottom chase close to each other to compress the molding material to cover the top electronic component on the top surface of the substrate, thereby forming a top encapsulation on the top surface of the substrate.

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

An integrated sensor component includes a chip carrier and a first semiconductor chip and a second semiconductor chip, wherein either both semiconductor chips are arranged on the chip carrier or (alternatively) the second semiconductor chip is arranged on the chip carrier and the first semiconductor chip is arranged on the second semiconductor chip (chip-on-chip). The integrated sensor component further includes a first sensor element integrated in the first semiconductor chip and a second sensor element integrated in the second semiconductor chip, as well as a housing formed by a potting compound, which has an opening. Both the first sensor element and the second sensor element are located within the opening so that they can interact with the atmosphere surrounding the sensor component.

A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate. The protective structure exposes one or more electrical contacts on a first surface of the at least one die. Respective terminals are formed on the one or more electrical contacts exposed by the protective structure. Related packages and fabrication methods are also discussed.