Patent classifications
H10W20/039
REDISTRIBUTION LINES WITH PROTECTION LAYERS AND METHOD FORMING SAME
A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
Barrier schemes for metallization using manganese and graphene
A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
Methods for reliably forming microelectronic devices with conductive contacts to silicide regions
Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).
Interconnects including graphene capping and graphene barrier layers
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.
AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES
Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
Method for manufacturing semiconductor structure with diffusion barrier layers
A method for manufacturing a semiconductor structure includes: a base provided with a contact hole is provided; an initial contact structure including a first diffusion barrier layer, a conductive layer and a second diffusion barrier layer stacked onto one another is formed on the base, the first diffusion barrier layer conformably covering the contact hole and covering part of a top surface of the base, the conductive layer covering first diffusion barrier layer and being filled in unoccupied space in the contact hole, the second diffusion barrier layer covering a side of the conductive layer away from first diffusion barrier layer, the initial contact structure outside the contact hole being provided with a groove exposing side walls of conductive layer and second diffusion barrier layer; a third diffusion barrier layer is formed on a side wall of initial contact structure exposed by the groove to obtain a target contact structure.
Methods of Forming Interconnect Structures in Semiconductor Fabrication
A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.