Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Disclosed are a silicon wafer and a method for filling a silicon via thereof, and belong to the field of superconducting quantum technologies. The method includes: obtaining a silicon wafer including at least one silicon via; providing a superconducting material on at least one side of the silicon wafer, the at least one side comprising a side where an opening of the silicon via is located; and heating and pressurizing the superconducting material to fill the superconducting material into the silicon via.

A self-filling method for high-aspect-ratio microvias of a substrate is provided, in which the substrate is activated with a coupling agent; a pasty nano-filler is applied onto a surface of the substrate, where the microvias in the substrate are self-filled with the pasty nano-filler through capillary action, the pasty nano-filler has a wetting angle of 30, and each of the microvias has an aspect ratio of 5-500:1 and a diameter of 1-100 m; and the coated substrate is subjected to sintering treatment.

A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.