A semiconductor device includes a substrate having an active region; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a via contact disposed in the first insulating layer and electrically connected to the active region; an interconnection structure disposed in the second insulating layer and electrically connected to the via contact; and an etch stop layer disposed between the first insulating layer and the second insulating layer. The etch stop layer includes an upper layer region, a lower layer region and an intermediate film between the upper layer region and the lower layer region. Each of the upper layer region and the lower layer region includes a compound that includes a first element, and an intermediate film includes a second element intermixed with the first element.

A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

A method for forming a contact structure includes: a base is provided and a sacrificial layer is formed on the base; the sacrificial layer is patterned to form a first gap exposing the base in the sacrificial layer; a dielectric layer is deposited in the first gap; the sacrificial layer is removed to form a second gap between dielectric layers; at least part of the dielectric layer at a periphery of the second gap is etched, to enlarge a size of an opening of the second gap.

A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

A package structure and a formation method of a package structure are provided. The method includes forming a protective layer to laterally surround an interconnection chip. The interconnection chip has a conductive via penetrating through a semiconductor substrate of the interconnection chip. The conductive via has a first portion and a second portion, and sidewall slopes of the first portion and the second portion are different. The second portion gradually becomes narrower along a direction towards the first portion. The method also includes forming a redistribution structure over the interconnection chip and the protective layer. The redistribution structure has multiple organic layers and multiple conductive features. The method further includes bonding a first chip-containing structure and a second chip-containing structure to the redistribution structure. Each of the first chip-containing structure and the second chip-containing structure partially covers the interconnection chip.

A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.