A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

A semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate, a gate dielectric, a gate electrode and dielectric structures. The gate dielectric has a top surface aligned with a top surface of the substrate. The gate electrode is disposed over the substrate and overlaps the gate dielectric. The gate electrode has first segments extending in parallel along a direction. The dielectric structures are disposed over the substrate, overlap the gate dielectric and extend in parallel along the direction. The dielectric structures and the first segments are arranged in an alternating pattern.

A transistor device includes: a semiconductor substrate having a doping concentration of a first dopant type; a highly doped source region of a second dopant type formed in a first surface of the semiconductor substrate; a first highly doped drain region of the second dopant type formed in the first surface; a gate structure arranged on the first surface and including a gate electrode formed on the first surface; and a first lightly doped region formed in the first surface and extending from the highly doped source region under the gate electrode. A channel region extends between the first lightly doped region and the highly doped drain region. The channel region has an average doping level of the first dopant type of n10.sup.x that varies by less than 0.5n10.sup.X between the first lightly doped region and the highly doped drain region along the lateral direction parallel to the first surface.

A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.