H10W40/28

Thermoelectric cooling for die packages

In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and methods of forming the disclosed microelectronic devices. In some embodiments, a disclosed device may include a first integrated device die. The disclosed device may further include a thermoelectric element bonded to the first integrated device die. The disclosed device may further include a heat sink disposed over at least the thermoelectric element. The thermoelectric element may be configured to transfer heat from the first integrated device die to the heat sink. The thermoelectric element directly may be bonded to the first integrated device die without an adhesive.

Tunable stack-up DIMM form factor cold plate with embedded peltier devices for enhanced cooling capability

An apparatus is described. The apparatus includes a metallic chamber having a first outer surface with first Peltier devices and a second outer surface with second Peltier devices. The first and second outer surfaces face in opposite directions such that the first Peltier devices are to cool first semiconductor chips that face the first outer surface and the second Peltier devices are to cool second semiconductor chips that face the second outer surface.

Tunable stack-up DIMM form factor cold plate with embedded peltier devices for enhanced cooling capability

An apparatus is described. The apparatus includes a metallic chamber having a first outer surface with first Peltier devices and a second outer surface with second Peltier devices. The first and second outer surfaces face in opposite directions such that the first Peltier devices are to cool first semiconductor chips that face the first outer surface and the second Peltier devices are to cool second semiconductor chips that face the second outer surface.

SEMICONDUCTOR PACKAGE WITH ACTIVE THERMAL MANAGEMENT
20260068670 · 2026-03-05 ·

A semiconductor package includes a substrate with metal conductors, integrated circuit (IC) chips disposed on the substrate and electrically connected with the metal conductors of the substrate, thermoelectric cooler (TEC) chips thermally connected with the IC chips and having thermoelectric coolers configured to cool respective zones of the semiconductor package, temperature sensors arranged to measure temperatures of the respective zones of the semiconductor package, and control circuitry to operate the thermoelectric coolers to cool the respective zones based on the measured temperatures of the respective zones. The control may include determining whether a temperature-indicative signal satisfies a thermal management action criterion, and performing a thermal management action corresponding to the thermal management action criterion in response to a determination that the temperature-indicative signal satisfies the thermal management action criterion.

Thermal and mechanical enhanced thermal module structure on heterogeneous packages and methods for forming the same

Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

Thermal and mechanical enhanced thermal module structure on heterogeneous packages and methods for forming the same

Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

Optical Transmitter
20260107771 · 2026-04-16 ·

Disclosed is a new configuration for improving temperature dependency of optical modulation output characteristics, and an implementation form adapted to each configuration in an optical transmitter in which an optical modulator and a driver IC thereof are integrally packaged. The optical transmitter includes: an optical modulator; a driver integrated circuit (driver IC) for supplying a modulation electrical signal for the optical modulator; a first Peltier device for controlling a temperature of the optical modulator; and a second Peltier device for controlling a temperature of the driver IC, in which the optical modulator and the driver IC are connected by a wire, and the temperature of the second Peltier device is set to be lower than the temperature of the first Peltier device.

Optical Transmitter
20260107771 · 2026-04-16 ·

Disclosed is a new configuration for improving temperature dependency of optical modulation output characteristics, and an implementation form adapted to each configuration in an optical transmitter in which an optical modulator and a driver IC thereof are integrally packaged. The optical transmitter includes: an optical modulator; a driver integrated circuit (driver IC) for supplying a modulation electrical signal for the optical modulator; a first Peltier device for controlling a temperature of the optical modulator; and a second Peltier device for controlling a temperature of the driver IC, in which the optical modulator and the driver IC are connected by a wire, and the temperature of the second Peltier device is set to be lower than the temperature of the first Peltier device.

Stacked random-access memory devices with refrigeration

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

Stacked random-access memory devices with refrigeration

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.