A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. More specifically, there may be provided includes a display device including an adhesive layer which includes a first portion and a second portion, wherein the first portion has higher adhesion than the second portion, and the second portion has lower adhesion than the first portion and includes high refractive particles so that a manufacturing process is simplified, and a method of manufacturing the same.

A semiconductor device according to an embodiment includes a semiconductor chip, a substrate, and an adhesive layer. The substrate supports the semiconductor chip. The adhesive layer is disposed between the semiconductor chip and the substrate. The adhesive layer bonds the semiconductor chip and the substrate. The adhesive layer has a first portion and a plurality of second portions. The first portion is formed of a first material. The plurality of second portions are formed of a second material. The second material has a greater elastic modulus and a greater thermal conductivity than the first material. The second portions are located inside the first portion. Each of the second portions is in contact with and connects the semiconductor chip and the substrate.

The invention relates to a substrate arrangement, to a method for producing an electronic assembly and to an electronic assembly. The substrate arrangement comprises (a) a metal foil comprising an upper side and an underside, (b) a silver layer arranged on the underside of the metal foil, and (c) a silver sinter layer arranged on the silver layer, wherein the silver layer has a thickness d(Ag) in the range of 20-1500 nm.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A packaging structure and a formation method thereof are provided. The packaging structure includes a carrier board, and a plurality of semiconductor chips adhered to the carrier board. Each semiconductor chip has a functional surface and a non-functional surface opposite to the functional surface, and a plurality of pads are formed on the functional surface of a semiconductor chip of the plurality of chips. A metal bump is formed on a surface of a pad of the plurality of pads, and a first encapsulation layer is formed on the functional surface. The packaging structure also includes a second encapsulation layer formed over the carrier board.

A copper paste for joining contains metal particles and a dispersion medium, in which the copper paste for joining contains copper particles as the metal particles, and the copper paste for joining contains dihydroterpineol as the dispersion medium. A method for manufacturing a joined body is a method for manufacturing a joined body which includes a first member, a second member, and a joining portion that joins the first member and the second member, the method including: a first step of printing the above-described copper paste for joining to at least one joining surface of the first member and the second member to prepare a laminate having a laminate structure in which the first member, the copper paste for joining, and the second member are laminated in this order; and a second step of sintering the copper paste for joining of the laminate.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An exemplary interconnect structure includes a first substrate, a second substrate vertically below the first substrate; and an underlayer structure between and in contact with the first and second substrates in which the underlayer structure between and in contact with the first and second substrates, a conductive connector between and electrically connecting the first and second substrates. The underlayer structure comprises an electromagnetic curable layer and a high thermal conductive layer and the underlayer structure laterally surrounds the conductive connector.