Patent classifications
H10W76/17
Display substrate and manufacturing method thereof, display module, and display apparatus
A display substrate has a display area and a peripheral area adjacent to the display area. The display substrate includes; a substrate; an antenna wiring disposed on a side of the substrate; the antenna wiring being located in the peripheral area and arranged around the display area; and at least one conductive layer located on the side of the substrate. The antenna wiring is arranged in a same layer as the at least one conductive layer.
Integrated circuit packages to minimize stress on a semiconductor die
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
THERMALLY ENHANCED EMBEDDED DIE PACKAGE
A method of fabricating an electronic device includes forming an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.
PACKAGES WITH STACKED DIES AND METHODS OF FORMING THE SAME
A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
FLIP-CHIP BONDING-BASED ANTENNA PACKAGING STRUCTURE AND ITS MANUFACTURING METHOD
A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.
Package structure and method for manufacturing the same
A package structure that includes a pair of substrates arranged to oppose each other so as to form an internal space; a bonding portion sealing the pair of substrates; an element is sealed in the internal space and surrounded by the pair of substrates; an adsorption layer within the internal space and opposing at least one substrate of the pair of substrates, the adsorption layer constructed to adsorbs at least hydrogen; and a diffusion-inhibiting layer between the at least one substrate and the adsorption layer, and in which hydrogen is more difficult to diffuse compared with in the at least one substrate.
Bottom package exposed die MEMS pressure sensor integrated circuit package design
A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
Semiconductor systems with anti-warpage mechanisms and associated systems, devices, and methods
Semiconductor systems having anti-warpage frames (and associated systems, devices, and methods) are described herein. In one embodiment, a semiconductor system includes (a) a printed circuit board (PCB) having a first side and a second side opposite the first side, and (b) at least one memory device attached to the PCB at the first side of the PCB. The semiconductor system further includes a frame structure attached to the PCB at the first side of the PCB and proximate the at least one memory device. The frame structure can be configured to resist warpage of the PCB, for example, when the semiconductor system is heated to attach the at least one memory device to the PCB.
PACKAGE STRUCTURE INCLUDING A PACKAGE LID WITH A BOTTOM LID PORTION AND TOP LID PORTION AND METHODS FOR FORMING THE SAME
A package structure includes a package substrate, a package module on the package substrate, an outer molding material layer on the package substrate around the package module, a thermal interface material (TIM) layer on the package module, and a package lid on the TIM layer and attached to the outer molding material layer. The package lid includes a bottom lid portion having a first coefficient of thermal expansion (CTE), and a top lid portion attached to the bottom lid portion and having a second CTE less than the first CTE.
PRESS CONTACT TYPE SEMICONDUCTOR DEVICE
According to one embodiment, a press contact type semiconductor device includes a first electrode, a second electrode, a pair of metal plates arranged between the first electrode and the second electrode, and a semiconductor element positioned between the pair of metal plates. The semiconductor element includes a semiconductor part with an electrode part on the upper surface of the semiconductor part. A metal sintered layer is between one of the metal plates and the electrode part. The surface area of the electrode part is less than the surface area of the metal plate.