H10D64/0135

Integrated circuit metal gate structure and method of fabricating thereof

A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

An exemplary method according to the present disclosure includes forming a first dielectric layer over a first conductive feature, forming a second dielectric layer over the first dielectric layer, forming a patterned mask over the second dielectric layer, performing a first etching process to form a trench extending through the first dielectric layer and the second dielectric layer to expose a top surface of the first conductive feature, where etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench, performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, where etchant of the second etching process further reacts with a part of a remaining portion of the first dielectric layer to cause a volume expansion of the remaining portion of the first dielectric layer, and forming a second conductive feature in the trench.

PREFERENTIALLY ORIENTED ELECTRODE FILM AND PREPARATION METHODS THEREOF
20260075883 · 2026-03-12 ·

The present invention provides a preferentially orientated electrode film and preparation methods thereof, relating to the technical field of thin film preparation, comprising a silicon-based substrate and a primary seed layer, a secondary seed layer and a bottom electrode layer grown sequentially on said substrate; said primary seed layer being an A.sub.xB.sub.1-xN film or an A.sub.3-xB.sub.1-xN film, wherein ACu, Fe; BPd, Pt; Ocustom-characterxcustom-character1; in which said secondary seed layer is made of one or more of the following films: chromium nitride film, titanium nitride film, tantalum nitride film, magnesium oxide film; and said bottom electrode layer is made of one or more of the following films: a platinum film, a titanium nitride film, a gold film, a strontium ruthenate film, or a niobium doped strontium titanate film, which has a preferential orientation in the (00/) crystallographic direction, to solve the problem that the existing films with (00/) preferential orientations are not obtainable on a Silicon based substrate.

Integrated dipole region for transistor

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high- dielectric layer on the interfacial layer, a dipole layer on the high- dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-k dielectric layer.