A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an apparatus includes a semiconductive region, an insulative region that is adjacent to the semiconductive region, and a conductive line that extends across the semiconductive region and at least a portion of the insulative region. The apparatus includes a contact structure that conjoins with the conductive line and that electrically couples the conductive line with the semiconductive region. The apparatus includes a footing structure that conjoins with the conductive line and that penetrates into the insulative region to anchor the conductive line with the insulative region.

A method is provided for manufacturing a semiconductor structure. The method includes providing a through hole penetrating a stacked layer and exposing a surface of an interconnecting conductive layer; forming a side wall material layer covering at least a side wall and a bottom of the through hole; forming a protective material layer covering the side wall material layer; performing thermal processing on the protective material layer, to cause the protective material layer to implement a material phase change process; etching and removing materials located at the bottom of the through hole to expose the surface of the interconnecting conductive layer, covering the side wall of the through hole, of the side wall material layer as a side wall layer, and taking a remaining protective material layer covering the side wall layer as a protective layer. Working performance of the semiconductor structure is improved.

A method of manufacturing a semiconductor device includes providing a structure including a first insulating pattern and a metal pattern disposed on a substrate, performing a cleaning process on the structure, exposing the structure to a reducing agent, forming, selectively, a passivation layer on the metal pattern, forming, selectively, a second insulating pattern on the first insulating pattern, and performing thermal processing on the structure.