An object is to provide a technique capable of reducing stress in the entire semiconductor device. The semiconductor device includes a plurality of sub-modules including a first sealing member, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductive plates of the plurality of sub-modules, connection members electrically connected to at least one of the conductive pieces of the plurality of sub-modules, and a second sealing member having lower hardness than the first sealing member, which seals the plurality of sub-modules, the insulating substrate, and the connection members.

A power semiconductor device according to the present invention is provided with: a first circuit body constituting an upper arm of an inverter circuit for converting a DC current into an AC current; a second circuit body constituting a lower arm of the inverter circuit; and a circuit board that has therein a through-hole in which the first circuit body and the second circuit body are disposed and that has an intermediate board between the first circuit body and the second circuit body. The intermediate board has an AC wiring pattern for transmitting the AC current, and the first circuit body and the second circuit body are connected to the AC wiring pattern so as to be in surface contact with the AC wiring pattern.

A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.

An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.

A semiconductor device includes: a first lead including a base portion; a semiconductor element mounted on a first side of the base portion in the thickness direction and including a first electrode; a second lead spaced apart from the base portion in a first direction perpendicular to the thickness direction; a first conductive member electrically bonded to the first electrode and the second lead; and a sealing resin. The first conductive member includes a first portion bonded to the first electrode via a conductive first bonding layer. The first portion includes a first surface and a second surface respectively facing the first side and a second side in the thickness direction. The first portion includes a plurality of first recesses that are recessed from the first surface and a plurality of second recesses that are recessed from the second surface.

The purpose of this invention is to provide a semiconductor device that prevents defects in semiconductor elements caused by differences in thermal expansion and maintains low electrical resistance by directly or indirectly laminating an FeNi alloy metal layer onto the front-surface or back-surface electrodes of the semiconductor element. In this invention, an FeNi alloy metal layer is directly or indirectly applied on the surface electrodes of the semiconductor element, and the semiconductor element is connected to a conductor through the FeNi alloy metal layer. Depending on the application, the Ni content of the FeNi alloy metal layer is set within the range of 36% to 45% by weight, and the thickness of the FeNi alloy metal layer is set within the range of 2 m to 20 m.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.

In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.