The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.

A display device includes a display area and a non-display area which is adjacent to the display area, a pad in the non-display area and connected to the display area, and an insulating layer on the pad. A portion of the pad is exposed outside of the insulating layer to define an exposed portion of the pad, the insulating layer includes a first portion having a first thickness and a second portion having a second thickness which is less than the first thickness, and the second portion of the insulating layer is between the exposed portion of the pad and the first portion of the insulating layer.

Provided is a semiconductor module including a stacked substrate in which a plurality of wiring layers are stacked, and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction.

Provided is a semiconductor module including a stacked substrate in which a plurality of wiring layers are stacked, and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction.

A semiconductor structure and semiconductor device are provided. The semiconductor structure includes a plurality of layers of memory modules stacked on an upper surface of the logic chip in a first direction which is perpendicular to the upper surface of the logic chip. Each storage module includes a plurality of memory chips stacked in a second direction which is parallel to the upper surface. Each memory chip in a top layer includes one second wireless communication part; and each memory chip in a non-top layer includes two second wireless communication parts arranged in the first direction and a wired communication part connected between the two second wireless communication parts. Two adjacent second wireless communication parts located on different memory chips in the first direction communicate with each other wirelessly; and each first wireless communication part communicates wirelessly with a closest second wireless communication part in a bottom memory chip.

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer embedded in the third insulating layer; and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are provided with different materials, wherein the second insulating layer and the fifth insulating layer are provided with a same material, and a thickness in a vertical direction between an upper surface of the fourth insulating layer and an upper surface of the third insulating layer is smaller than a thickness of the second insulating layer in the vertical direction.

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer embedded in the third insulating layer; and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are provided with different materials, wherein the second insulating layer and the fifth insulating layer are provided with a same material, and a thickness in a vertical direction between an upper surface of the fourth insulating layer and an upper surface of the third insulating layer is smaller than a thickness of the second insulating layer in the vertical direction.