The present application discloses a method for manufacturing a NAND flash, comprising: step 1, sequentially form a floating gate dielectric layer and a first polysilicon layer; step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, wherein a first doping concentration of the second polysilicon layer is less than a target doping concentration; step 3, forming a pattern transfer mask layer; step 4, patterning the pattern transfer mask layer; step 5, performing gate etching, wherein the first and second polysilicon layers subjected to the gate etching respectively form a polysilicon floating gate and the polysilicon control gate; step 6, forming a first spacer, wherein the first spacer in a storage area fully fills a first interval area; and step 7, performing self-aligned ion implantation to increase a doping concentration of the polysilicon control gate to the target doping concentration.

An integrated circuit includes a dielectric isolation structure formed at a surface of a semiconductor substrate and a polysilicon resistor body formed on the dielectric isolation structure. The polysilicon resistor body includes an N-type dopant having an N-type dopant concentration, nitrogen having a nitrogen concentration, and carbon having a carbon concentration. The sheet resistance of the resistor body is greater than 5k/square.

Methods of electrostatically clamping a glass substrate to a platen are disclosed. In one embodiment, a conductive layer is applied to the glass substrate, wherein the conductive layer provides the requisite clamping force. The transistor is then fabricated on the glass substrate. The conductive layer may be transparent, such that the bottom surface of the transistor may be inspected. In another embodiment, a lower polysilicon layer and oxide layer are deposited on the glass substrate. The transistor is then fabricated above the oxide layer.

Aspects include a transistor having a gate region with a uniform gate length and a body contact region abutted to a conduction channel under the gate region to improve mitigation of the kink effect, and related methods. The transistor includes the conduction channel formed from a semiconductor layer. A source region and a drain region of the transistor are formed on opposite sides of the conduction channel in the semiconductor layer. A gate region is formed adjacent to the conduction channel. The gate region has a gate length and a gate width. The transistor has a body contact region having a second polarity and directly adjacent to the second side of the conduction channel creating a body interface between the body contact region and the conduction channel. The gate length is uniform throughout the entire gate width including where the body contact region is directly adjacent to the conduction channel.

The present invention provides a semiconductor device and a method of fabricating the same, which includes: providing a semiconductor substrate having a first patterned region and a second patterned region and performing floating-gate poly-Si deposition on the semiconductor substrate thereby forming a first poly-Si layer, wherein the first patterned region has a higher feature density than the second patterned region; performing ion implantation on the first poly-Si layer and forming an oxide layer over a top surface of the first poly-Si layer; with the oxide layer in the second patterned region being protected, etching the oxide layer in the first patterned region; performing a CMP process on the first poly-Si layer in the first patterned region and on the oxide layer and the first poly-Si layer in the second patterned region; and forming the semiconductor device on the basis of the first poly-Si layer that has undergone the CMP process.