In this semiconductor device, an emitter electrode of a power semiconductor element includes a first sub-electrode provided in a region including a central portion of a front surface of a semiconductor substrate and a second sub-electrode provided in a region not including the central portion of the front surface of the semiconductor substrate. A first bonding wire connects the first sub-electrode and an emitter terminal. A second bonding wire connects the second sub-electrode and the emitter terminal. First and second voltage detectors detect voltages between the emitter terminal and the first and second sub-electrodes, respectively. It is possible to separately detect degradation of both the first bonding wire that degrades in an early period and the second bonding wire that degrades in a terminal period.

A semiconductor arrangement includes a substrate including a substrate metallization having line sections which are arranged so as to be electrically insulated from one another. A semiconductor element is connected to a first line section of the substrate metallization and has a contact surface on a side facing away from the substrate. A wiring element connects the contact surface of the semiconductor element to the substrate. The wiring element includes a first connecting section connecting the contact surface to a second line section of the substrate metallization, and a second connecting section connects the contact surface to a third line section of the substrate metallization, with the second line section and the third line section of the substrate metallization being designed such that the first connecting section and the second connecting section have an asymmetrical current flow during operation of the semiconductor arrangement.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.