An electronic package is provided in which an electronic structure is bonded onto a carrier structure via a plurality of conductive elements, where each of the conductive elements is connected to a single contact of the electronic structure via a plurality of conductive pillars. Therefore, when one of the conductive pillars fails, each of the conductive elements can still be electrically connected to the contact via the other of the conductive pillars to increase electrical conductivity.

According to one aspect, a semiconductor package structure is provided. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, the first semiconductor chip includes at least one first conductive structure, the first conductive structure includes a first connection structure extending along the first direction, a second connection structure extending along the first direction, and an interconnection structure between the first connection structure and the second connection structure in the first direction, and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first bump connection layer between two adjacent ones of the first semiconductor chips in the first direction, the first bump connection layer includes at least one first bump structure, and the first bump structure is coupled with each of the first conductive structures in the two adjacent first semiconductor chips.

An electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; a second insulating layer disposed on the first metal bump; a metal layer, wherein the first insulating layer is disposed between the second insulating layer and the metal layer; a second metal bump disposed between the metal layer and the first insulating layer, wherein the second metal bump electrically connects to the first metal bump; a third insulating layer disposed between the second metal bump and the first insulating layer, wherein the third insulating layer includes an opening exposing a portion of the second metal bump; and a fourth insulating layer disposed between the third insulating layer and the first insulating layer, wherein a portion of the fourth insulating layer extends and is disposed in the opening to contact the second metal bump.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A chip structure having an interconnect and a manufacturing method thereof include a buffer layer formed between an upper metal structure and a passivation layer under the upper metal structure so as to prevent fractures, such as cracks, from occurring in the passivation layer due to difference of stress between the upper metal structure and the passivation layer.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

A metal bump containing structure is provided which has a substantially flat top surface and enhanced coplanarity with other like metal bump containing structures. The metal bump containing structures include a metal bump having a curved top surface, and a first metal liner located along an outermost sidewall and present at least partially on the curved top surface of the metal bump.