Patent classifications
H10W72/223
Method for manufacturing semiconductor device including forming opening in resist of the semiconductor device
A method for manufacturing a semiconductor device includes providing a semiconductor element having electrode terminals; forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminals and a second surface opposite to the first surface; forming an opening in the resist, which covers the electrode terminals by inserting protrusions of a mold into the resist above the electrode terminals; curing the resist by applying energy to the resist; and widening the opening in a radial direction of the opening. The resist is cured in a state where the second surface of the resist faces an inner surface of the mold with a gap between the second surface of the resist and the inner surface of the mold.
Semiconductor device assembly interconnection pillars and associated methods
In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.
PACKAGING DEVICE INCLUDING BUMPS AND METHOD OF MANUFACTURING THE SAME
A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.