Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.

Provided are a security device and a substrate.

Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and the first die and the second die are in a stacked structure. The stacked structure has the one or more metal layers of the first die disposed between the active layer of the first die and the active layer of the second die.

Integrated circuit (IC) protections that prevent exposure or examination of integrated circuitry through backside analysis include a layer or mesh of an electrically conductive, electromagnetic radiation blocking material disposed over a backside of an IC device to prevent backside analysis. An electrically conductive conduit couples the material to a node of the integrated circuitry to provide a signal and/or voltage reference to the node through the layer/mesh. If the layer/mesh is tampered with, the integrated circuitry loses the voltage reference or signal thereby disabling the integrated circuitry. The IC device may include detection circuitry to monitor the node and to generate an alert and/or disable the circuitry upon tampering. The IC device may further include a support substrate, where a substrate between the material/mesh and the integrated circuitry is sufficiently thin that the IC device would be mechanically weak if the support substrate were removed.

A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.

A physically unclonable function (PUF) device comprises a plurality of conductors, at least some of which are arranged so that they interact electrically and/or magnetically with one another. A media surrounds at least a portion of each of the conductors, and circuitry is configured for applying an electrical challenge signal to at least one of the conductors and for receiving an electrical output from at least one of the other conductors to generate an identifying response to the challenge signal that is unique to the device. The media comprises a plurality of interactive regions, the interactive regions having an electrical and/or magnetic response characteristic which is permanently altered in response to a predetermined environmental event, and the identifying response is altered with the response characteristic.

A microelectronic circuit package may include one or more operative channels, each of the one or more operative channels containing a reactive material, and a seal covering at least a portion of the one or more operative channels. At least one of the one or more operative channels has a maximum width of less than about 100 microns. The seal is non-reactive with the reactive material. Also disclosed are methods of manufacturing a microelectronic circuit package comprising at least one operative channel containing a reactive material.

A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

A system may include an integrated circuit (IC) package. The IC package may include one or more IC die hosting one or more circuits, and an interposer. The interposer may be coupled to the one or more IC die via an interconnection layer. The interposer may include one or more electrically active devices configured to provide one or more security functions to secure the one or more circuits. The interposer may be coupled to a backside power of the IC package. In some embodiments, the backside power of the IC package may include one or more backside power delivery networks.