The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

A method of forming a semiconductor device includes a number of operations. A dielectric layer is formed over a plurality of nanostructures arranged in a vertical manner and an isolation structure adjacent the nanostructures. The dielectric layer is nitridated. A vertical portion of the nitridated dielectric layer over a sidewall of the nanostructure is removed, wherein a first horizontal portion of the nitridated dielectric layer remains over the isolation structure, and a second horizontal portion of the nitridated dielectric layer remains over a topmost one of the nanostructures. A source/drain region is formed through the second horizontal portion of the nitridated dielectric layer and the nanostructures. A gate structure is formed and wraps around the nanostructures.

A method of manufacturing an integrated circuit. This method includes forming an epitaxial material comprising single crystal piezo material overlying a surface region of a substrate to a desired thickness and forming a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material. Also, the method includes forming a topside landing pad metal and a first electrode member overlying a portion of the epitaxial material and a second electrode member overlying the topside landing pad metal. Furthermore, the method can include processing the backside of the substrate to form a backside trench region exposing a backside of the epitaxial material and the landing pad metal and forming a backside resonator metal material overlying the backside of the epitaxial material to couple to the second electrode member overlying the topside landing pad metal.

Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

The present disclosure generally relates to semiconductor processing for forming a gate oxide layer and a corresponding semiconductor device. In an example, a semiconductor device includes a semiconductor substrate, a gate oxide layer, a gate electrode, a first source/drain region, and a second source/drain region. The gate oxide layer is on the semiconductor substrate. The gate oxide layer has a thickness less than or equal to 25 Angstroms. The gate oxide layer includes nitrogen and includes a peak concentration of nitrogen that is equal to or greater than 20 atomic percent. The gate electrode is over the gate oxide layer. The first source/drain region is in the semiconductor substrate. The second source/drain region is in the semiconductor substrate. The first source/drain region and the second source/drain region are on opposing lateral sides of the gate electrode.