An electronic device is provided. The electronic device includes a substrate, an active element, a first insulation layer, and a detection element. An active element is disposed on the substrate. A first insulation layer is disposed on the active element. A detection element is disposed on the first insulation layer. The detection element comprises a lower electrode disposed on the first insulation layer, an active layer disposed on the lower electrode, an upper electrode disposed on the active layer, and the lower electrode is a part of a conductive layer. The first insulation layer has a recess, and the recess does not overlap with the conductive layer in a normal direction of the substrate.

A substrate including a two-dimensional array of semiconductor dies and a rectangular grid of trenches that laterally extend along dicing channel regions may be provided. The rectangular grid of trenches may be filled with an elastic dielectric fill material. A combination of the two-dimensional array of semiconductor dies and a grid-shaped portion of the elastic dielectric fill material filling the rectangular grid of trenches may be diced along the dicing channel regions. A plurality of elastically padded semiconductor dies is formed. Each of the elastically padded semiconductor dies includes a respective singulated semiconductor die that includes semiconductor devices and metal bump structures located on dielectric material layers, and further includes an elastic protective material portion including a portion of the elastic dielectric fill material and laterally surrounding the dielectric material layers.

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor. The method includes steps as follows: A first substrate having a central region and an edge region is provided; a first dielectric layer covering the central region and the edge region is formed, where the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; a first filling layer of a first dielectric layer covering the edge region is formed; and the first filling layer is planarized, and a first edge region flush with the surface of the first dielectric layer in the central region is formed on the surface of the first filling layer.

A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.