According to one embodiment, a semiconductor memory device includes: a first chip including a substrate defining a first region and a second region; and a second chip contacting the first chip in a first direction, the second chip being electrically connected to the first chip via a plurality of connection pads at a boundary region. The second chip includes a memory cell array, the memory cell array including a source line, word lines below the source line, and a memory pillar. The second chip further includes contacts extending in the first direction and each electrically connected to one of the connection pads, a conductor pattern contacting upper ends of the contacts, and a first interconnect extending above the conductor pattern and electrically connected to the conductor pattern.

A high bandwidth memory according to an example embodiment may include a base die, and a semiconductor stack on the base die. The semiconductor stack may include a plurality of semiconductor dies, which may be stacked in a vertical direction. Each of the plurality of semiconductor dies may include a plurality of memory dies arranged in a horizontal direction.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

A memory device includes a memory layer and a circuit layer. The memory layer includes first to third regions arranged in a first direction. The circuit layer includes first and second transfer regions, and first and second sense amplifier regions. The first and second transfer regions are shifted in the first direction and arranged in a second direction. In a third direction, the first sense amplifier region overlaps the first region, and the second sense amplifier region overlaps the second region. The first sense amplifier region and the first transfer region are arranged in the first direction, and the second sense amplifier region and the second transfer region are arranged in the first direction.

A high bandwidth memory including a first semiconductor stack including a plurality of first semiconductor dies stacked in a vertical direction; a glass core on the first semiconductor stack; and a second semiconductor stack on the glass core, the second semiconductor stack including a plurality of second semiconductor dies stacked in the vertical direction.

A semiconductor memory device includes: a plurality of first conductive layers arranged in a first direction and extending in a second direction intersecting with the first direction and a third direction intersecting with the first direction and the second direction; and a memory structure extending in the first direction, the memory structure including a first semiconductor layer opposed to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer contains single-crystallized silicon and an impurity. The impurity contain: a first metallic element that is able to form silicide; and a second metallic element constituting a metal material having a linear expansion coefficient larger than a linear expansion coefficient of a silicon material.

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.