A manufacturing method for a semiconductor device according to an embodiment includes a first step deforming a bump of a semiconductor element by applying a first load to the semiconductor element to press the bump onto a circuit board and applying either no ultrasonic vibration or ultrasonic vibration with a first strength to the bump and a second step, after the first step, bonding the bump to a pad of the circuit board by applying a second load to the semiconductor element to press the bump and applying ultrasonic vibration with a second strength stronger than the first strength to the bump.

A semiconductor package may include: a first wiring structure including a first wiring pattern and a first wiring insulating layer surrounding the first wiring pattern; a first semiconductor chip above the first wiring structure; a second semiconductor chip above the first wiring structure and spaced apart from the first semiconductor chip in a horizontal direction; an adhesive layer including a first portion on an upper surface of the first semiconductor chip, and further including a second portion on an upper surface of the second semiconductor chip; a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip, the second semiconductor chip, and the adhesive layer; and a heat dissipation member on an upper surface of each of the molding member and the adhesive layer.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (die) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 m/1.5 m. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

A semiconductor package and a method for manufacturing a semiconductor package includes a base substrate including a first surface and a second surface, a first contact pad disposed on the first surface of the base substrate, a first solder resist layer disposed on the first surface of the base substrate, a second solder resist layer covering a portion of an upper surface of the first solder resist layer, and a first connector disposed in the first opening area and the second opening area. The first solder resist layer covers a side surface and a portion of an upper surface of the first contact pad, and defines a first opening area on the first contact pad. The first connector is in contact with the first contact pad. A first width of the first opening area is smaller than a second width of the second opening area.

A bonding structure of a semiconductor package device that physically and electrically connects between a semiconductor chip and a package substrate or between a package substrate and a board, the bonding structure includes a solder; a main pad that faces the solder; and an electrically conductive support structure that is connected between the solder and the main pad, the electrically conductive support structure including a sub pad bonded to the solder, the sub pad being spaced apart from the main pad and facing the main pad, and at least one leg extending from the sub pad to the main pad.