A memory device is disclosed. The memory device includes a transistor. The memory device includes a resistor electrically coupled to the transistor, the transistor and the resistor forming an electrical fuse (eFuse) memory cell. The memory device includes a plurality of interconnect structures formed over a source/drain structure of the transistor. The memory device includes a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures. The resistor is formed of titanium nitride (TiN).

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

Integrated circuit structures having anti-fuse structures, and methods of fabricating integrated circuit structures having anti-fuse structures, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A first gate structure is over the first vertical stack of horizontal nanowires, the first gate structure including a first gate dielectric and a first gate electrode completely surrounding a channel region of each nanowire of the first vertical stack of horizontal nanowires. The integrated circuit structure also includes a second vertical stack of horizontal nanowires. A second gate structure is over the second vertical stack of horizontal nanowires, the second gate structure including a second gate dielectric and a second gate electrode only partially surrounding a channel region of each nanowire of the second vertical stack of horizontal nanowires.