An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

An electronic network device includes a package substrate, an Integrated Circuit (IC) mounted on the package substrate, and a plurality of interconnection terminals disposed on a surface of the package substrate. The interconnection terminals include multiple pairs of signal terminals and multiple ground terminals. The interconnection terminals are arranged in a hexagonal grid in which (i) a given interconnection terminal is surrounded by six other interconnection terminals, and (ii) propagation paths between signal terminals that do not belong to a same pair are at least partially blocked by the ground terminals.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

An electrical structure and a method of manufacturing an electrical structure are provided. The electrical structure includes a substrate, a first insulation layer, a second insulation layer and an electrical contact. The first insulation layer and the second insulation layer are disposed over the substrate. The electrical contact extends through the first insulation layer and the second insulation layer. The electrical contact includes a first portion disposed in the first insulation layer and a second portion disposed in the second insulation layer. The first portion has a first width, and the second portion has a second width. A ratio of a difference between the first width and the second width to the first width is less than 10%.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a conductive structure including a conductive concave layer positioned on the substrate and including a top surface having a V-shaped cross-sectional profile; and a conductive filling layer positioned on the conductive concave layer; and a top conductive layer positioned on the conductive structure. The conductive filling layer includes germanium or silicon germanium.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

A semiconductor structure includes: a high-speed circuit module including a clock signal with a frequency greater than a first threshold; a first conductive metal layer including power conductive wires extending along a first direction and arranged at intervals, and the power conductive wires being electrically connected with the high-speed circuit module; and a redistribution layer located above the first conductive metal layer and including power pads and electrical wires connected with the power pads, in which the power pads are located at one side of the high-speed circuit module, a projection of the power pads does not overlap with that of the high-speed circuit module, the electrical wires include a first electrical wire region where the electrical wires are repeatedly bent, the first electrical wire region at least partially covers the high-speed circuit module, and the electrical wires are used for electrically connecting the power conductive wires and power pads.