A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.

A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A multilayer wiring connection structure and a method for manufacturing the same are provided. The multilayer wiring connection structure includes a first insulating film positioned on a substrate, a first wiring positioned within the first insulating film, a second insulating film positioned on the first wiring, and a second wiring positioned within the second insulating film and in contact with the first wiring. The first wiring comprises a trench having at least one anisotropically etched portion and at least one isotropically etched portion under the second wiring, and the second wiring comprises an extension filling the trench.

The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

A three dimensional semiconductor device is disclosed. The tree dimensional semiconductor device includes a word line stack over a substrate and a channel pillar structure passing through the word line stack in a vertical direction perpendicular to a top surface of the substrate. The channel pillar structure includes a channel structure. The channel structure includes a blocking layer, a trap layer, a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure has a pillar shape.

A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.