A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.

Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package.

Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.

A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.

A leadframe (10) comprises: a functional area (12) having a first standard electrode potential; and a non-functional area (14) adjacent to the functional area (12) and including a protective layer, the protective layer (16) having a second standard electrode potential lower than the first standard electrode potential and acting as a sacrificial anode to protect the functional area (12) as a cathode from corrosion/oxidation. Embodiments of the present disclosure may help to protect functions of the leadframe (10) from affections of corrosion/oxidization, etc.

One example discloses a degradation circuit, including: a first set of structures configured to be coupled to a semiconductor package; a second set of structures, coupled to the first set of structures, and configured to be coupled to the package; wherein together the first and second set of structures form a Wheatstone bridge within a degradation detection element; and a controller, coupled to the degradation detection element, and configured to set an operational state of an integrated circuit (IC) within the package based on the degradation detection element.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A power electronics module, having a PCB having power semiconductors arranged on connecting regions of an uppermost layer of said PCB, wherein the PCB has a preset dimension to arrange a preset maximum number of power semiconductors thereon. A lead frame arranged above the power semiconductors provides three-dimensional power and control routing, and includes a drain-source connection to connect to a drain-source contact of the PCB, and a load-source connection opposite the drain-source connection via the power semiconductors that is formed from a plurality of subregions, each of which can be brought into electrical contact with the power semiconductors, and a gate- and kelvin-source terminal, which are arranged above the load-source connection and have been brought into electrical contact with the power semiconductors. At least one dummy chip consisting of an electrically nonconductive material is arranged on each of the connecting regions that are not populated by power semiconductors.