A lead frame connects a metal wiring and an electrode of a case. A seal material is filled in the case. The lead frame includes a first joint portion joined to the metal wiring, a second joint portion joined to the electrode, and a connection portion connecting the first joint portion and the second joint portion. The connection portion includes an inclined portion inclined with respect to the upper surface of the insulating substrate on a cross-section across an extension direction of the lead frame, a first non-inclined portion provided between the inclined portion and the first joint portion, and a second non-inclined portion provided between the inclined portion and the second joint portion. Slits are provided on both sides of the lead frame at a boundary of the first non-inclined portion and the inclined portion and a boundary of the second non-inclined portion and the inclined portion.

A lead frame includes a base comprising a bearing surface for bearing a chip. The bearing surface includes a soldering region, with a solder layer arranged in the soldering region. The solder layer is configured for fixing the chip on the bearing surface. The lead frame includes a groove provided on the bearing surface in a thickness direction of the base. The groove is located outside the soldering region and surrounds at least part of the soldering region along the outer periphery of the soldering region for receiving solder paste overflowed from the soldering region. A depth of the groove is based on a thickness of the base. A packaging structure including the lead frame and a packaging method using the lead frame are also provided.

An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

A power semiconductor package includes a first substrate assembly with a power semiconductor die defining a high-side power switch, a second substrate assembly arranged parallel to the first substrate assembly which has a power semiconductor die defining a low-side power switch, and a power terminal assembly. The power terminal assembly includes a power terminal substrate arranged between the first and the second substrate assembly, a high-side drain power terminal electrically connected to an electrical drain circuit of the high-side power switch, a low-side source power terminal electrically connected to an electrical source circuit of the low-side power switch, and a mid-point power terminal electrically connected to an electrical source circuit of the high-side power switch and to an electrical drain circuit of the low-side power switch. The high-side drain power terminal, the low-side source power terminal, and the mid-point power terminal are each arranged on the power terminal substrate.

A semiconductor device having a fan-out package structure includes a semiconductor element having a first electrode pad and a second electrode pad on a front surface, a sealing material covering a side surface of the semiconductor element and a redistribution layer covering the front surface of the semiconductor element and a part of the sealing material. The redistribution layer includes an insulation layer, a first redistribution wire and a second redistribution wire. At least a part of the first redistribution layer is disposed above a boundary between the side surface of the semiconductor element and the sealing material. The second redistribution wire is electrically connected to the second electrode pad, and at least has a part that extends to a position outside of a contour of the semiconductor element over the first redistribution wire. The second redistribution wire is electrically independent of the first redistribution wire.

A module includes an assembly of a semiconductor device die coupled to a lead frame. A board is disposed below the lead frame. The board includes a plated-through hole (PTH) aligned with an opening in the lead frame above the board. The module further includes a mold body encapsulating at least a portion of the assembly. The mold body includes a through-mold via (TMV) aligned with the opening in the lead frame and with the PTH. The PTH is physically accessible from outside the mold body through the TMV and the opening in the lead frame.

A chip package structure includes a die pad, input/output pads, a chip, first bonding wires, a molding compound, a solder resist layer, first solder balls and second solder balls. The input/output pads are configured around the die pad. The chip is configured on the die pad. The first bonding wires are electrically connected to the chip and the input/output pads. The molding compound covers the chip, the die pad, the input/output pads and the first bonding wires, and exposes a first lower surface of the die pad and a second lower surface of each input/output pad. The solder resist layer is configured on the first lower surface of the die pad and has multiple openings exposing a portion of the die pad. The first solder balls are respectively configured in the openings of the solder resist layer, and the second solder balls are respectively configured on the input/output pads.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A semiconductor device includes: a semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; and a sealing resin covering the semiconductor element, the island lead, the terminal lead, and the wire. The terminal lead includes a base member having an obverse surface facing in a thickness direction of the terminal lead, and a metal layer located between the obverse surface and the wire. The base member has a greater bonding strength with respect to the sealing resin than the metal layer. The obverse surface includes an opposing side facing the island lead. The obverse surface includes a first portion that includes at least a portion of the opposing side and that is exposed from the metal layer.

An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.