Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.

A semiconductor package includes a film substrate that includes a chip region, a first edge region, and a second edge region. The semiconductor package includes a semiconductor chip on the chip region, where the semiconductor chip includes first conductive bumps adjacent to the first edge region and second conductive bumps adjacent to the second edge region. The semiconductor package includes first pads and second pads on the first edge region, and first lines that electrically connect ones of the first pads to ones of the first conductive bumps. The second pads are dummy pads. A first set of the second pads and a second set of the second pads are spaced apart from each other in the second direction with the first pads therebetween. The first set of second pads includes ten or more consecutive second pads with no first pads therebetween.

A chip mounted substrate may include: a film-type substrate including: a first edge region and a second edge region opposing in a first direction; and a third edge region and a fourth edge region connecting the first edge region and the second edge region and opposing in a second direction intersecting the first direction; and a semiconductor chip on the film-type substrate. The film-type substrate may include: an insulating film; chip bonding pads electrically connected to the semiconductor chip; external connection pads electrically connected to the chip bonding pads; and test pads electrically connected to the chip bonding pads and the external connection pads. The test pads may be in at least three of the first edge region, the second edge region, the third edge region, and the fourth edge region.