A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

A method of manufacturing a display apparatus includes forming a semiconductor layer on a substrate, forming an insulating layer on the semiconductor layer, forming a photoresist pattern on the insulating layer, forming, by etching the insulating layer, a contact hole exposing at least a portion of the semiconductor layer, and performing a primary cleaning of the insulating layer in which the contact hole is formed using a cleaning gas including a fluorine-containing gas and a hydrogen-containing gas.

Methods and apparatus for forming an integrated circuit device, including performing a spin-cleaning step at a first rotational speed on a semiconductor substrate supporting the integrated circuit device at an intermediate stage of manufacturing. A rinse fluid is then dispensed over a top surface of the substrate. A rotational speed of the substrate is increased with a constant acceleration no greater than 125 revolutions per minute per second (rpm/s) from the first rotational speed to a second rotational speed. The second rotational speed is maintained for a rinse fluid extraction period. The rotational speed is then reduced to zero.

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.