A device comprises a non-insulator structure, a dielectric layer, a metal via, a metal line, and a dielectric structure. The dielectric layer is over the non-insulator structure. The metal via is in a lower portion of the dielectric layer. The metal line is in an upper portion of the dielectric layer. The dielectric structure is embedded in a recessed region in the lower portion of the dielectric layer. The dielectric structure has a tapered top portion interfacing the metal via.

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

Certain embodiments of the present disclosure relate to a sensor assembly including a housing having a first channel configured to flow a gas in a first direction and a second channel configured to flow the gas in a second direction. The housing is configured to couple to a gas flow assembly. A substrate is disposed within the housing. The substrate has an outer region, an inner region within the first channel, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. A sensor die is coupled to the inner region of the substrate, having an electrical connection to the electrical contact pads. The sensor die is disposed within a gas flow path of the first channel.

A sensor assembly includes a substrate having an outer region, an inner region, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. The sensor assembly further includes a housing coupled to the substrate at the middle region or the outer region to provide a hermetic seal. The sensor assembly further includes a sensor die bonded to the substrate at the inner region. A metal bond bonds electrodes of the sensor die to the electrical contact pads. The metal bond includes platinum, and/or one or more metals selected from tin, indium, copper, aluminum, and/or nickel.

A method of processing a substrate that includes: selectively depositing a self-assembled monolayer (SAM) on a metal line of the substrate, the SAM being in contact with the metal line, a surface of the substrate further including a first dielectric material that surrounds the metal line; selectively depositing a second dielectric material over the first dielectric material; forming a dielectric layer by depositing a third dielectric material over the second dielectric material and the SAM; and patterning the dielectric layer.

A sensor assembly includes a substrate including one or more electrical contact pads on at least an inner region of the substrate. The sensor assembly further includes a housing coupled to the substrate by a flange, the flange to provide a hermetic seal between the housing and the substrate. The housing is configured to be coupled to a fluid flow channel at a first end of the housing and at a second end of the housing. The sensor assembly further includes a sensor die coupled to the substrate at the inner region via the electrical contact pads. The sensor die is aligned to the substrate via one or more alignment features.

A semiconductor device includes a substrate. The semiconductor device further includes a conductive structure in the substrate. The semiconductor device further includes an etch stop layer over the substrate. The semiconductor device further includes an interlayer dielectric (ILD) over the etch stop layer. The semiconductor device further includes a dual damascene conductive element in the ILD, wherein the dual damascene conductive element extends through the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.

A method of manufacturing a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around an outer perimeter of a substrate composed of a dielectric material. The patterned electrode layer includes multiple electrodes around the outer perimeter of the substrate and gaps between adjacent electrodes. The method further includes depositing a dielectric layer over at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.