A method for manufacturing a semiconductor device is disclosed. The method includes forming a mask layer containing a first metal and a first halogen on a film to be processed. The method includes patterning the mask layer. The method includes performing a treatment on the mask layer to decrease the concentration of the first halogen. The method includes processing the film using the treated mask layer as a mask.

An example of an etching method according to the present disclosure, includes: performing a first process which includes forming a first layer containing halogen or holding the substrate in a gas atmosphere containing halogen; and performing a second process which includes removing a portion of the first layer and a portion of the substrate under the portion of the first layer by supplying the portion of the first layer with ions sourced from a solid material.

A semiconductor memory device manufacturing method includes the following steps. A bit line structure is formed in a memory array area of a substrate. A gate structure is formed in a periphery area of the substrate. A dielectric layer is formed over the bit line structure and the gate structure. A lower hard mask layer is formed over the dielectric layer. An etch process diagnostic signal layer is formed over the lower hard mask layer. An upper hard mask layer is formed over the etch process diagnostic signal layer. A main etching step is performed to form a first via hole towards the bit line structure and a second via hole towards the gate structure until the upper hard mask layer is removed to expose the etch process diagnostic signal layer.

A semiconductor structure and a method for fabricating the semiconductor structure are provided in the present disclosure. The method includes providing a substrate, wherein the substrate includes a plurality of first regions to-be-etched extending along a first direction; a first region to-be-etched includes a central region and an edge region adjacent to each of two sides of the central region; and a material layer to-be-etched is on the substrate; forming a plurality of discrete initial mask structures on the material layer to-be-etched; etching initial mask structures at the edge region till a surface of the material layer to-be-etched is exposed to form a plurality of mask structures; using the plurality of mask structures as a mask, etching the material layer to-be-etched to form a plurality of discrete layers to-be-etched; and removing layers to-be-etched at the central region till a surface of the substrate is exposed.

The present disclosure relates to high selectivity doped hardmask films, as well as methods of providing and using such films. In particular examples, the high selectivity doped hardmask film can be employed as a hardmask, an intermediate layer, or a coverage layer.

A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

A semiconductor device fabrication method includes forming a substrate having first and second regions therein, with different densities of active regions in the first and second regions. A cell trench is formed, which defines cell active regions in the first region, and a peripheral trench is formed, which defines peripheral active regions in the second region. A first insulating layer is formed in the cell trench and the peripheral trench. A mask is selectively formed, which covers the first insulating layer in the first region and exposes the first insulating layer in the second region. A second insulating layer is formed on the first insulating layer in the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process. The first insulating layer is exposed in the first region by removing the mask. A third insulating layer is formed on the first insulating layer in the first region and on the second insulating layer in the second region.

A method for fabricating semiconductor devices is disclosed. The method includes forming a stack over a substrate. The method includes forming a hardmask layer over the stack, the hardmask layer comprising a first tungsten containing sub-layer, and at least one compressive sub-layer and at least one tensile sub-layer. The method includes forming a patternable layer over the hardmask layer. The method includes etching the hardmask layer according to the patternable layer.

A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a plurality of first mask layers over the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers over the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; patterning the plurality of second mask layers to form a cut pattern; forming a first aperture modification layer on the cut pattern to define a plurality of first openings overlapping the plurality of first mask layers along a third direction substantially orthogonal to the first direction and the second direction; patterning the plurality of first mask layers to form an active region definition pattern; and patterning the substrate to define an active region by the active region definition pattern.

Embodiments of improved process flows and methods are provided to pattern a semiconductor substrate using direct self-assembly (DSA) of metalate salt ionic liquid crystals (ILCs) having metalate anions. After self-assembly of the metalate salt ILCs into ordered structures, an oxidation process is used to remove the organic components of the ordered structures and convert the metalate anions into metal oxide patterns. In addition to providing a robust metal oxide pattern, which can be transferred to the underlying substrate, the process flows and methods disclosed herein enable ILCs to be used as pitch multipliers in advanced patterning techniques.