H10W72/01361

Display device and method of manufacturing the same

Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. More specifically, there may be provided includes a display device including an adhesive layer which includes a first portion and a second portion, wherein the first portion has higher adhesion than the second portion, and the second portion has lower adhesion than the first portion and includes high refractive particles so that a manufacturing process is simplified, and a method of manufacturing the same.

Sintered Power Electronic Module

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
20260060146 · 2026-02-26 · ·

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

METHOD FOR MANUFACTURING SINTER BONDING FILM, AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR PACKAGE

A method for manufacturing sinter bonding film, includes: preparing a resin formulation; preparing a metal filler mixture; mixing the resin formulation and the metal filler mixture, thereby preparing a paste for film manufacturing; and manufacturing a sinter bonding film by using the paste for film manufacturing. The metal filler mixture includes a metal powder and a reducing agent, copper metal (Cu) corresponds to respective particles in the metal powder, and the surface of the respective particles in the metal powder undergoes acid treatment or non-treatment.

SUBSTRATES WITH SPACERS, INCLUDING SUBSTRATES WITH SOLDER RESIST SPACERS, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS

Substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. Electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. The substrate further includes a solder resist spacer disposed on the solder resist layer. The solder resist spacer can have a height corresponding to a thickness of the electronic device. The solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.

INTEGRATED CIRCUIT PACKAGE AND METHOD

An integrated circuit package and the method of forming are provided. The integrated circuit package may include a first redistribution structure, a first bridge die over the first redistribution structure, a first encapsulant around the first bridge die, a second redistribution structure over the first bridge die and the first encapsulant, a first logic die, a second logic die, and a first input/output (I/O) die over the second redistribution structure, and a second encapsulant around the first logic die, the second logic die, and the first I/O die. The first I/O die may be between the first logic die and the second logic die in a top-down view. The first bridge die may electrically connect the first redistribution structure to the second redistribution structure. The first I/O die may electrically connect the first logic die to the second logic die.